The present invention is generally directed to amplifier circuits and, more specifically, to a cascaded amplifier having better immunity to power supply noise and absolute supply level.
Signal amplifiers are used in a very wide range of electronic devices to boost the power of a signal, usually for transmission or reception purposes. Signal amplifiers are frequently implemented as integrated circuits that are used in wireless phones, radios, televisions, network cards, and the like. One very common type of signal amplifier is the cascaded current gain (Gm1/Gm2) amplifier.
A cascaded Gm1/Gm2 amplifier typically contains several NMOS differential amplifier stages cascaded in series. Each NMOS stage comprises n-type metal-oxide-silicon (NMOS) transistors used as loads and a differential pair of NMOS transistors. At the end of a series of M cascaded NMOS differential amplifier stages, there is typically a simple differential amplifier with an NMOS differential pair and p-type MOS (PMOS) loads. The advantage of this type of amplifier configuration is very high gain and a wide bandwidth with a large output compliance under most conditions.
Unfortunately, under some conditions, this type of configuration has a disadvantage in that the power supply limits directly affect the output compliance range. As the positive supply voltage changes, the sources of the NMOS load devices in the last Gm1/Gm2 amplifier track the change. The DC bias voltage on the NMOS differential pair in the last stage are subject to large voltage swings directly caused by supply voltage changes. This is a disadvantage in that the supply limits directly affect the output compliance range.
There is therefore a need in the art for signal amplifiers having very high gain, wide bandwidth, and a large output compliance even under less than ideal conditions. In particular, there is a need for an improved cascaded Gm1/Gm2 amplifier containing M cascaded NMOS differential amplifier stages that has better immunity to changes in the supply voltage.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an amplifier comprising: 1) a plurality of cascaded NMOS differential amplifier stages, wherein a first one of the plurality of cascaded NMOS differential amplifier stages is coupled to at least one input signal; 2) a PMOS differential amplifier stage having a first input coupled to a first NMOS differential output of a last one of the plurality of cascaded NMOS differential amplifier stages and a second input coupled to a second NMOS differential output of the last cascaded NMOS differential amplifier stage, wherein the PMOS differential amplifier comprises a first diode-connected PMOS load transistor having a gate and a drain connected to ground and a second diode-connected PMOS load transistor having a gate and a drain connected to ground; and 3) an output differential amplifier stage comprising: a) load transistors comprising a third PMOS transistor having a gate and a drain connected together and a source connected to a power supply rail and a fourth PMOS transistor having a gate coupled to the third PMOS transistor gate and a source connected to the power supply rail; and b) a differential transistor pair comprising a first NMOS transistor having a gate coupled to a source of the first diode-connected PMOS load transistor and a drain coupled to a drain of the third PMOS transistor and a second NMOS transistor having a gate coupled to a source of the second diode-connected PMOS load transistor and a drain coupled to a drain of the fourth PMOS transistor.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.